MCBSTM32EXL【PDF 311/995 页】BOARD EVALUATION FOR STM32F103ZE

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RM0008

13.4.10

TIM1&TIM8 counter (TIMx_CNT)

Address offset: 0x24

Reset value: 0x0000

Advanced-control timers (TIM1&TIM8)

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CNT[15:0]

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Bits 15:0

CNT[15:0] : Counter value

13.4.11

TIM1&TIM8 prescaler (TIMx_PSC)

Address offset: 0x28

Reset value: 0x0000

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Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency (CK_CNT) is equal to f CK_PSC / (PSC[15:0] + 1).

PSC contains the value to be loaded in the active prescaler register at each update event

(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger

controller when configured in “reset mode”).

13.4.12

TIM1&TIM8 auto-reload register (TIMx_ARR)

Address offset: 0x2C

Reset value: 0x0000

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Bits 15:0 ARR[15:0] : Prescaler value

ARR is the value to be loaded in the actual auto-reload register.

Refer to the Section 13.3.1: Time-base unit on page 256 for more details about ARR update

and behavior.

The counter is blocked while the auto-reload value is null.

Doc ID 13902 Rev 9

311/995

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